Thursday, 14 June 2018

MIPS I6500-F FIRST HIGH PERFORMANCE 64 BIT MULTI-CLUSTER CPU IP TO RECEIVE ISO 26262 AND LEC 61508 CERTIFICATION

Scalable Multi-threaded, Multi-core, Multi-cluster IP core designed for safety critical systems in an autonomous age, raises the bar on Functional Safety

SANTA CLARA, Calif., June 12 (Bernama-GLOBE NEWSWIRE) -- MIPS, provider of the widely used MIPS processor architecture and IP cores for licensing, today announced that its I6500-F CPU IP core, designed as a Safety Element out of Context (SEooC), is the first high performance 64 bit multi-cluster CPU IP to receive formal certification of compliance for ASIL B [D], based on ISO 26262: 1st edition 2011 (&DIS 2nd Edition 2018) and IEC 61508 SIL 2. The core was certified by Resiltech, a leader in certification of safety-related products for automotive and industrial applications.

“The I6500-F has been successfully assessed to be compliant to the latest ISO 26262 [including DIS ISO 26262, 2nd edition] and IEC 61508 safety standard and the MIPS team has followed the safety requirements, not only to address quantitative requirements for random failures for ASIL B [D], but also to achieve compliance regarding the systematic failure requirements. The safety compliance and the resulting safety cases will be of great value to the component vendors,” said Dr. Francesco Rossi, Automotive Safety Solutions Manager, Resiltech s.r.l
http://mrem.bernama.com/viewsm.php?idm=32077

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